ECE/CS 757 Spring 2009 Readings and Reviews

Last Updated: 1/23/2009

Most links will only work for computers in the wisc.edu domain. Please contact mikko@engr.wisc.edu for the password to the beta book chapters.

Review Guidelines

Students are expected to have completed the assigned readings before attending class and actively participate in discussions.
To facilitate great class discussions, students must submit an email review of selected papers by 10am before the lecture for which the paper is assigned. Late reviews will not be accepted.
I encourage students are encouraged to form study groups to discuss the papers before writing their reviews, but each student must write their own independent review.
Reviews should be submitted as PDF or plain text via the learn@uw dropbox by the deadline (10am) on the date indicated below.
Detailed contents of each review: Paper title, authors, year; your name and ID number; a short summary of the paper (e.g. problem and proposed solutions); identification of a point that should be emphasized in lecture; an exam question based on this paper.
Reviews will be graded on a scale of Excellent (10 points), Satisfactory (7 points), and Unsatisfactory (3 points). Most reviews will get a 7. Reviews that are too long will automatically receive an Unsatisfactory grade.

Introduction

James E. Smith, Beta Chapter 1.
G. Amdahl, “The Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities,” Spring Joint Computer Conference, 1967, pp. 483-485.
K. Olukotun, et al., “The Case for a Single-Chip Multiprocessor,” ASPLOS-7, October 1996.
Review due 1/26: Mark Hill and Mike Marty, Amdahl's Law in the Multicore Era, IEEE Computer, July 2008

Multiprocessor Software and ISA

James E. Smith, Beta Chapter 2
Leslie Lamport, How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs, IEEE Trans. on Computers, September 1979, pp. 690-691.
H. Sutter and J. Larus, Software and the Concurrency Revolution, ACM Queue, September 2005.
LLNL OpenMP Tutorial.
LLNL pThreads Tutorial.
LLNL MPI Tutorial.
Review due 1/30: L. Barroso et al., Memory System Characterization of Commercial Workloads, ISCA 1998.
Review due 2/2: J. Mellor-Crummey and M. Scott, Algorithms for Scalable Synchronization on Shared Memory Multiprocessors, ACM TOCS 1991 (skim results in Section 4).

Cores, Multithreading, Multicore

James E. Smith, Beta Chapter 3
D. Marr et al., "Hyper-Threading Technology Architecture and Microarchitecture," Intel Technology Journal, Feb. 2002.
J. M. Borkenhagen et al., "A Multithreaded PowerPC Processor for Commercial Servers," IBM Journal of Research and Development, 2000.
Creeger, M., “Multicore CPUs for the Masses” , ACM Queue, pp. 64-65, Sept. 2005.
L. Barroso et al. Piranha: A Scalable Architecture Based on Single Chip Multiprocessing, Proc. 27^th International Symposium on Computer Architecture, June 2000.*
M. Zhang and K. Asanovic, Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
Review due 2/9: Li, Y., et al., “CMP Design Space Exploration Subject to Physical Constraints”, HPCA-12, pp. 17-28, Feb. 2006.
Review due 2/16: Kumar, R., et al., “Heterogeneous Chip Multiprocessors”, IEEE Computer, pp. 32-38, Nov. 2005.

MP Memory Systems

James E. Smith, Beta Chapter 4
Sarita V. Adve and Kourosh Gharachorloo, “Shared Memory Consistency Models: A Tutorial,” IEEE Computer, 29(12):66-76, December 1996.
M. D. Hill, “Multiprocessors Should Support Simple Memory Consistency Models,” IEEE Computer, Aug. 1998, pp. 28-34.
C. P. Thacker, L. C. Stewart, and E. H. Satterthwaite Jr., “ Firefly: A Multiprocessor Workstation,” IEEE Transactions on Computers, Aug. 1988, pp. 909-920.
J. Archibald, “Cache coherence protocols: Evaluation using a multiprocessor simulation model,” ACM Trans. Comp. Systems, pp. 273-298,1986.
P. Sweazey and A. J. Smith, A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus, Proc. Thirteenth International Symposium on Computer Architecture, June 1986.
Review due 2/23: C. Natarajan, B. Christenson, and F. Briggs, “A Study of Performance Impact of Memory Controller Features in Multi-Processor Server Environment,” Proc. of the 3rd Workshop on Memory Perf. Issues, June 2004 pp. 80-87.
M. Herlihy and J. E. Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures, ISCA-93.
L. Hammond, et al., "Transactional Memory Coherence and Consistency," Proc. International Symposium on Computer Architecture, June 2004.
R. Rajwar, et al., “Virtualizing Transactional Memory,” Proc. International Symposium on Computer Architecture, June 2005.
Review due 2/27: B. Saha, A.-R. Adl-Tabatabai, Q. Jacobson, “Architectural Support for Software Transactional Memory,” 39^thInt. Symp. on Microarchitecture, Dec. 2006, pp. 185-196.

Case Studies

NOTE: Postponed to Midterm #2. Not included on midterm #1.

J. Laudon and D. Lenoski, The SGI Origin: A CCNUMA Highly Scalable Server, ISCA-97.
CANCELLED -- NO REVIEW (Review was due 3/2): Keltcher, C.N., McGrath, K.J., Ahmed, A., and Conway, P., “The AMD Opteron processor for multiprocessor servers”, IEEE Micro, 2003.
A. Charlesworth, et al., Gigaplane XB -- Extending the Ultra Enterprise family Hot Interconnects V, July 1997.
B. Sinharoy et al., “Power5 System Microarchitecture,” IBM Journal of Research and Development, July 2005, pp. 505-521.
F. Briggs, et al., “Intel 870: a building block for cost-effective, scalable servers,” IEEE Micro, March-April 2002, pp. 36-47.
CANCELLED -- NO REVIEW (Review was due 3/6): R. Clapp and T. Lovett, STiNG: A CC-NUMA Computer System for the Commercial Marketplace, ISCA-96.